This invention relates to semiconductor nonvolatile memory devices, and particularly to a semiconductor nonvolatile memory device suitable for use in electrically erasing the contents and rewriting new data.
There are known semiconductor nonvolatile memory devices for storing a program and data such as an erasable and programmable read only memory (hereinafter, abbreviated EPROM) of which the contents, or information can be erased by ultraviolet ray and an electrically erasable and programmable read only memory (hereinafter, abbreviated EEPROM) of which the contents can be electrically erased.
The EPROM has a small memory cell area and thus is suitable for a large capacity, but it needs a package with a window through which an ultraviolet ray is radiated for erasing its contents. Moreover, since data is written in the memory by a programmer, it is required to be removed from the system upon rewriting.
Meanwhile, the EEPROM can be electrically rewritten within the system, but its memory cell area is about 1.5 to 2 times as large as that of the EPROM; therefore, it is not suitable for a large capacity.
Recently, a compromise between both types, which is called a flash EEPROM (a simultaneous electrical erasure EEPROM) has been developed. This flash EEPROM (simultaneous electrical erasure EEPROM) is a nonvolatile semiconductor memory device having the function of electrically erasing data of one chip or a group of memory cells at a time, and of which the size of the memory cell area can be made comparable to that of the EPROM.
FIG. 1 shows the memory cell of the flash EEPROM which was disclosed by Kume in the Proceedings of the IEDM (International Electron Device Meeting), Dec., 6-9, 1987, in an article entitled, "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure", pp. 560-563. This cell has the stacked gate structure quite similar to that of the normal EPROM.
This memory makes the writing operation by injecting the hot carriers generated in the vicinity of a drain-1 junction into a floating gate 2 as does the EPROM. The threshold voltage as measured from a control gate 4 of the memory cell is increased as a result of performing the writing.
On the other hand, for the erasing operation, the control gate 4 is grounded and a high voltage is applied to a source 3, thereby producing a high electric field between the floating gate 2 and the source 3 so that the electrons accumulated on the floating gate 2 are pulled toward the source 3 through a thin oxide film 5 by the tunneling which occurs. The threshold voltage as measured from the control gate 4 is decreased as a result of performing the erasing.
For the reading operation, to make sure that weak writing is substantially prevented, a low voltage of about 1 V is applied to the drain 1, a voltage of about 5 V is applied to the control gate 4, and the large and small values of the channel current are assigned to logic "1" and logic "0", respectively. In FIG. 1, 6 represents a p-type silicon substrate, 7 and 7' n-type diffusion layers, 8 a low impurity concentration n-type diffusion layer and 9 a p-type diffusion layer.
V. N. Kynett and others have developed a 256 k bit memory using memory cells similar to that shown in FIG. 1. The memory is reported in the IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct., 1988, pp. 1157-1162. This memory is capable of performing simultaneous electrical erasure.
FIG. 3 shows a memory cell array which the inventors of the present invention have schemed and considered in an effort to develop a memory cell array capable of information erasure on a memory block-by-memory block basis, by the use of memory cells similar to that shown in FIG. 1. In FIG. 3, the memory cell array is divided into memory blocks B1, B2, . . . , so that information erasure is possible on a memory block-by-memory block basis. Thus, the circuit structure shown in FIG. 3 is not known.
In addition, G. Samachisa and others published a paper directed to a memory cell, formed of a MOSFET, such as, shown in FIG. 2 of the present application, for the simultaneous electrical erasure EEPROM, in the 1987 IEEE International Solid-State Circuit Conference, pp. 76-77.
The operation of this memory cell is substantially the same as that of the memory cell shown in FIG. 1, but is different in that the erasing (in addition to the writing and reading) is also made on the drain side. In accordance with such a memory cell structure, an array of memory cells as shown in FIG. 4 is formed in which the array is divided into memory blocks B11 to B13 respectively associated with data lines D11 to D13. Data lines D11 to D13 are electrically connected to the drains of the corresponding MOSFETS. Therefore, selective erasing can be made for each block at a time, and thus in this point, a memory device having this type of memory cell array is easy to use. In FIG. 4, M21 to M38 represent memory cells, and W11 to W16 word lines.
These memory devices mentioned above, however, do not consider the program disturbance mechanism (or characteristic). The program disturbance characteristic means the change of the threshold value of a MOSFET constituting a memory cell when a high voltage is applied to the gate of the MOSFET, and when no voltage is applied to the drain. The time in which the program disturbance mechanism is occurring in one memory cell (for example, an unselected memory cell during a writing operation) connected to a certain word line is normally the total time in which other memory cells connected to the same word line undergo a writing operation.
For example, in FIGS. 3 and 4, the program disturbance time of the memory M1 (M21) is a sum of the time in which the memory M2 (M22) is written and the time in which the memory M3 (M23) is written.
However, the program disturbance time in which the writing is performed on a memory block-by-memory block basis is different from the above-mentioned disturbance time. If one block B1 (B11) performs no rewriting after writing data once, and if the other blocks B2, B3 (B12, B13) perform a rewriting operation repeatedly, the program disturbance time amounts to the writing time for blocks B2, B3 (B12, B13) multiplied by the number of times that the rewriting is performed.
By the way, G. Verma reported the reliability of the memory cell developed by Mr. Kynett and others, in the 1988 IEEE Reliability Physics Symposium, pp. 158-166. According to this report, after the repetition of rewriting, there occurs a phenomenon in which there is an increase of the adverse effect attributed to the program disturbance characteristic. Thus, this phenomenon of an increase in the adverse effect becomes serious when the program disturbance time is lengthened, as described above.
Also, in the prior art, the circuit arrangement of the memory array within the chip encounters the following problem.
FIG. 5 is a plan view of a geometrical layout of a memory cell array which the inventors of the present invention have schemed with respect to the memory cell structure of FIG. 1 and the circuit structure of FIG. 3. Thus, the layout of FIG. 5 is not known. This plan view is similar to that of the ordinary EPROM. As illustrated, data lines D1 to D4 are made of a metal layer and formed in the longitudinal direction, or in the direction perpendicular to that of word lines W1 to W5, and thus common source lines CS1, CS2 are made of a metal layer and are formed in parallel with the data lines. The common source lines for use in the memory blocks, respectively, originate from a side of the memory array (for example, the upper side in FIG. 5) opposite the side thereof on which a column selection switch MOS FET and a sense amplifier are arranged.
FIG. 6 shows the front face (or main surface) of, for example, a rectangular shaped semiconductor chip depicting the whole circuit arrangement of the memory device. In this figure, the memory array is shown as two separate memory cell arrays, that is, memory cell array M-ARAY 1 for external terminals (or pads) I/O 0 to I/O 3 and memory cell array M-ARAY 2 for external terminals (or pads) I/O 4 to I/O 7. At this time, as in FIG. 5, the word lines are formed in the lateral direction (or horizontal direction in the figure) and the data lines in the longitudinal direction (or vertical direction in the figure). A row address decoder XDCR for selecting and controlling the word lines is disposed in a central plan view area on the front face of the semiconductor chip between the two memory cell arrays M-ARAY 1 and M-ARAY 2, thereby facilitating selection and control of both parts of the memory array at a time. A column address decoder YDCR is formed under the row address decoder XDCR, as shown in FIG. 6, that is in an area on the front face of the semiconductor chip adjacent the central area thereof and near that one of the pair of longer peripheral edges at which the external terminals I/O 0 to I/O 7 are provided. The column selection switch MOS FET and the sense amplifiers YGSNS 1, YGSNS 2 are formed under the memory array parts M-ARAY 1, M-ARAY 2, as shown in FIG. 6, that is, in an area on the front face of the chip adjacent to the corresponding memory cell arrays M-ARAY 1 and M-ARAY 2 and near the same longer peripheral edge of the device as that with respect to the column address decoder YDCR. The erase decoders ECR 1, ECR 2 are formed in areas of the chip adjacent the memory array parts M-ARAY 1, M-ARAY 2, respectively, and near the other one of the pair of longer peripheral edges of the front face of the chip.
Generally, when data of the memory in the system realized on a single substrate is rewritten for each block, the selection of blocks is made by a high-order bit address. For example, for a 1-M bit memory for reading and writing each 8 bits at a time, the address signal is formed of 17 bits of A16 to A0. If the memory array of this memory device is divided into 4 blocks, two bits of A16 and A15 are, preferably, used for selecting a block to be erased.
However, the bonding pads through which signals are supplied are generally arranged as shown in FIG. 6. The flash EEPROM, in general, takes substantially the same arrangement as the EPROM. A 1-M bit flash EEPROM seems to take such an arrangement as illustrated. In FIG. 6, the pads are labeled according to use/function at their positions. The flash EEPROM is different from the 1-M bit EPROM in that it has a terminal EE. The reason for this arrangement is that the arrangement of input pins of the packaged memory is normally standardized. The circuit arrangement within the chip is limited chiefly by the I/O terminals, or the column selection switch MOSFET and the sense amplifiers YGSNS 1, YGSNS 2 are disposed under the memory array, or near the I/O terminals. The higher-order, or more-significant bit address of A16 and A15 is disposed on the upper side. For minimizing the length of the wiring from each input/output pad to circuits, since the column address decoder YDCR, the column selection switch MOS FET, and sense amplifiers YGSNS 1, YGSNS2 are disposed under the memory array, it is natural that the high-order address of A16 and A15 is used for the row selection address, and that a low-order address is used for the column selection address.
In this case, when the memory blocks are formed along the data lines as shown in FIG. 5, the blocks to be erased are selected by the column address, or the lower-order address. If selection is made differently, that is, using the high-order address, the length of the wiring from the input and output terminals becomes long, and particularly the reading speed is decreased due to the delay in the wiring.
The method of electrically erasing the above flash EEPROM (simultaneous electrical erasure type EEPROM) (electrically erasable and programmable read only memory) is described in the IEEE Journal of Solid State Circuits, vol. 23, No. 5, October, 1988, pp. 1157-1162. When the electrons within the floating gate are pulled toward the source by use of tunneling, the sources of all memory cells are connected together. By a single application of a high voltage to the common source line, it is possible to electrically erase the entire memory array at a time.
Also, it is necessary, upon the start of an erasing operation, to charge the electrostatic capacitance associated with the common source line and, upon ending of an erasing operation, to discharge it.